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Freescale Semiconductor Advance Information
Document Number: MC33972 Rev. 9.0, 4/2007
Multiple Switch Detection Interface with Suppressed Wake-Up
The 33972 Multiple Switch Detection Interface with Suppressed Wake-Up is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). The device also features a 22-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX output pin for the MCU to read. The 33972 device has two modes of operation, Normal and Sleep. Normal mode allows programming of the device and supplies switch contacts with pullup or pulldown current as it monitors switch change of state. The Sleep mode provides low quiescent current, which makes the 33972 ideal for automotive and industrial products requiring low sleep state currents. Features * * * * * * * * * * Designed to Operate 5.5 V VPWR 26 V Switch Input Voltage Range -14 V to VPWR, 40 V Max Interfaces Directly to MPU using 3.3 V / 5.0 V SPI Protocol Selectable Wake-Up on Change of State Selectable Wetting Current (16 mA or 2.0 mA) 8 Programmable Inputs (Switches to Battery or Ground) 14 Switch-to-Ground Inputs Typical Standby Current - VPWR = 100 A and VDD = 20 A Active Interrupt (INT) on Change-of-Switch State Pb-Free Packaging Designated by Suffix Code EW
33972 33972A
MULTIPLE SWITCH DETECTION INTERFACE
DWB SUFFIX EW SUFFIX (Pb-FREE) 98ARH99137A 32-PIN SOICW
ORDERING INFORMATION
Device MC33972DWB/R2 MC33972EW/R2 MCZ33972AEW/R2 -40C to 125C 32 SOICW Temperature Range (TA) Package
VDD VBAT VBAT SP0 SP1 VBAT SP7 Power Supply LVI VDD VDD WAKE SI SCLK CS SO INT AMUX MOSI SCLK CS MISO INT AN0 Enable Watchdog Reset MCU
33972
VPWR
SG0 SG1
SG12
SG13
GND
Figure 1. 33972 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Device 33972 33972A Switch Input Voltage Range -14 to 38 VDC -14 to 40 VDC Reference Location 6 6
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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V VPWR VPWR 16.0 mA SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 16.0 mA To + 2.0 4.0 V - SPI Ref mA Comparator 5.0 V VPWR 5.0 V To + 4.0 V - SPI Ref Comparator WAKE
WAKE Control
SP0
VPWR
VPWR, VDD, 5.0 V POR Bandgap Sleep PWR
VPWR VDD GND
2.0 mA
16.0 mA
To + 2.0 4.0 V - SPI mA Ref Comparator
VPWR VPWR 16.0 mA 2.0 mA
SP7 5.0 V Oscillator and Clock Control VPWR
5.0 V Temperature Monitor and Control 5.0 V 125 k
VPWR VPWR 16.0 mA SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 VPWR VPWR 16.0 mA 2.0 mA 2.0 mA
SG0
SPI Interface and Control
VDD 125 k INT
INT Control
VDD MUX Interface 40 A CS
VDD
SCLK SI SO
SG13
To + 4.0 V - SPI Ref Comparator
+
VDD
Analog Mux Output
-
AMUX
Figure 2. 33972 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
GND SI SCLK CS SP0 SP1 SP2 SP3 SG0 SG1 SG2 SG3 SG4 SG5 SG6 VPWR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SO VDD AMUX INT SP7 SP6 SP5 SP4 SG7 SG8 SG9 SG10 SG11 SG12 SG13 WAKE
Figure 3. 33972 Pin Connections Table 2. 33972 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 1 2 3 4 5-8 25 - 28 9 - 15, 18 - 24 16 17 29 30 31 32 Pin Name GND SI SCLK CS SP0 - 3 SP4 - 7 SG0 - 6, SG13 - 7 VPWR WAKE INT AMUX VDD SO Formal Name Ground SPI Slave In Serial Clock Chip Select Programmable Switches 0-7 Switch-to-Ground Inputs 0 - 13 Battery Input Wake-Up Interrupt Analog Multiplex Output Voltage Drain Supply SPI Slave Out Definition Ground for logic, analog, and switch to battery inputs. SPI control data input pin from MCU to 33972. SPI control clock input pin. SPI control chip select input pin from MCU to 33972. Logic [0} allows data to be transferred in. Programmable switch-to-battery or switch-to-ground input pins. Switch-to-ground input pins. Battery supply input pin. Pin requires external reverse battery protection. Open drain wake-up output. Designed to control a power supply enable pin. Open-drain output to MCU. Used to indicate input switch change of state. Analog multiplex output. 3.3 / 5.0 V supply. Sets SPI communication level for SO driver. Provides digital data from 33972 to MCU.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS VDD Supply Voltage
CS, SI, SO, SCLK, INT, AMUX WAKE (1)
(1)
Symbol
Value
Unit
VDC - - - - - - VESD -0.3 to 7.0 -0.3 to 40 -0.3 to 50 -0.3 to 45 -14 to 40 6.0 2000 2000 200 750 500 VDC VDC VDC VDC MHz V
(2)
VPWR Supply Voltage
(1)
VPWR Supply Voltage at -40C(1) Switch Input Voltage Range Frequency of SPI Operation (VDD = 5.0 V) ESD Voltage (3) Human Body Model Machine Model Charge Device Model Corner Pins Interior Pins THERMAL RATINGS Operating Temperature Ambient Junction Case Storage Temperature Power Dissipation (TA = 25C) (4) Thermal Resistance Junction to Ambient Junction to Lead Peak Package Reflow Temperature During Reflow
(5), (6)
Applies to all non-input pins
C
TA TJ TC TSTG PD RJA RJL TPPRT - 40 to 125 - 40 to 150 - 40 to 125 - 55 to 150 1.7 74 25 Note 6. C
C
W
C/W
Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. ESD data available upon request. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), and ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 4. 5. 6. Maximum power dissipation at TJ = 150C junction temperature with no heat sink used. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics Characteristics noted under conditions 3.1 V VDD 5.25 V, 8.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic POWER INPUT Supply Voltage Supply Voltage Range Quasi-Functional (7) Fully Operational Supply Voltage Range Quasi-Functional Supply Current All Switches Open, Normal Mode, Tri-State Disabled Sleep State Supply Current Scan Timer = 64 ms, Switches Open Logic Supply Voltage Logic Supply Current All Switches Open, Normal Mode Sleep State Logic Supply Current Scan Timer = 64 ms, Switches Open SWITCH INPUT Pulse Wetting Current Switch-to-Battery (Current Sink) Pulse Wetting Current Switch-to-Ground (Current Source) Sustain Current Switch-to-Battery Input (Current Sink) Sustain Current Switch-to-Ground Input (Current Source) Sustain Current Matching Between Channels on Switch-to-Ground I/Os ISUS(MAX) - ISUS(MIN) ISUS(MIN) X 100 IOFFSET VOFFSET -10 VOL - VOH VDD - 0.1 VTH 3.70 VIN -14 -14 TLIM
(9) (7)
Symbol
Min
Typ
Max
Unit
V VPWR (QF) VPWR (FO) VPWR (QF) IPWR (ON) - IPWR (SS) 40 VDD IDD - IDD(SS) - 10 20 0.25 0.5 A 3.1 70 - 100 5.25 V mA 2.0 4.0 A 5.5 8.0 26 - - - 8.0 26 38/40 mA
IPULSE IPULSE ISUSTAIN ISUSTAIN IMATCH
12 12 1.8 1.8 -
15 16 2.0 2.0 2.0
18 18 2.2 2.2 4.0
mA mA mA mA %
Input Offset Current When Selected as Analog Input Offset Voltage When Selected as Analog V(SP&SGINPUTS) to AMUX Output Analog Operational Amplifier Output Voltage Sink 250 A Analog Operational Amplifier Output Voltage Source 250 A Switch Detection Threshold 33972 / 33972A Switch Input Voltage Range 33972 33972A Temperature Monitor (8), (9) Temperature Monitor Hysteresis
-2.0
1.4 2.5
2.0 10
A mV
mV 10 - 4.0 - - - 10 30 V - V 4.3 V 38 40 185 15
155 5.0
C C
TLIM(HYS)
Notes 7. Device operational. Table parameters may be out of specification. 8. Thermal shutdown of 16 mA pullup and pulldown current sources only. 2.0 mA current source / sink and all other functions remain active. 9. This parameter is guaranteed by design but is not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V VDD 5.25 V, 8.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic DIGITAL INTERFACE Input Logic Voltage Thresholds (10) SCLK, SI, Tri-State SO Input Current 0 V to VDD
CS Input Current CS = VDD CS Pullup Current CS = 0 V
Symbol
Min
Typ
Max
Unit
VINLOGIC ISCLK, ISI, ISO (TRI) ICS
0.8 -10
- -
2.2 10
V A A
-10 ICS 30 VSO (HIGH) VDD - 0.8 VSO (LOW) -
(11)
-
10 A
- -
100 V VDD V 0.4 20 100 VDD V 0.4 100 5.3 V 0.4 V A V pF A V
SO High-State Output Voltage I SO (HIGH) = -200 A SO Low-State Output Voltage I SO (HIGH) = 1.6 mA Input Capacitance on SCLK, SI, Tri-State SO
INT Internal Pullup Current INT Voltage INT = Open Circuit INT Voltage
- - 40 - 0.2 40 4.3 0.2
CIN - V INT (HIGH)
- 15 VDD - 0.5
V INT (LOW) - I WAKE (PU) V WAKE (HIGH) 4.0 V WAKE(LOW) - V WAKE(MAX) - - 40 20
I INT = 1.0 mA
WAKE Internal Pullup Current WAKE Voltage WAKE = Open Circuit WAKE Voltage
I WAKE = 1.0 mA
WAKE Voltage
Maximum Voltage Applied to WAKE Through External Pullup Notes 10. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK. 11. This parameter is guaranteed by design but is not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V VDD 5.25 V, 8.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic SWITCH INPUT Pulse Wetting Current Time Interrupt Delay Time Normal Mode Sleep Mode Switch Scan Time Calibrated Scan Timer Accuracy Sleep Mode Calibrated Interrupt Timer Accuracy Sleep Mode DIGITAL INTERFACE TIMING VPWR 0.2 V Falling Edge of CS to Rising Edge of SCLK Required Setup Time Falling Edge of SCLK to Rising Edge of CS Required Setup Time SI to Falling Edge of SCLK Required Setup Time Falling Edge of SCLK to SI Required Hold Time SI, CS, SCLK Signal Rise Time (14) SI, CS, SCLK Signal Fall Time
(14) (15) (16) (12)
Symbol
Min
Typ
Max
Unit
t PULSE (ON) t INT-DLY
15
16
20
ms s
- t SCAN t SCAN TIMER - t INT TIMER - 100
5.0 200
16 300 s %
-
10 %
-
10
Required Low-State Duration on VPWR for Reset (13)
t RESET - t LEAD 100 t LAG 50 t SI (SU) 16 t SI (HOLD) 20 t R (SI) t F (SI) t SO (EN) t SO (DIS) t VALID - - - - - - 5.0 5.0 - - 25 - - - 55 55 55 - - - - - - - 10
s
ns
ns
ns
ns
ns ns ns ns ns
Time from Falling Edge of CS to SO Low Impedance Time from Rising Edge of CS to SO High Impedance Time from Rising Edge of SCLK to SO Data Valid Notes 12. 13. 14. 15. 16. 17.
(17)
These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface. This parameter is guaranteed by design but not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
t LEAD
t LAG
SCLK
0.7 VDD 0.2 VDD
tSI(SU) tSI(HOLD)
SI
0.7 VDD 0.2 VDD
MSB IN
tSO(EN)
t VALID
0.7 VDD 0.2 VDD
tSO(DIS)
SO
MSB OUT
LSB OUT
Figure 4. SPI Timing Characteristics
VPWR VDD WAKE INT CS Wake-Up From Closed Switch Power-Up Normal Mode Tri-State Command (Disable Tri-State) Sleep Command Sleep Mode Normal Mode Sleep Command Sleep Mode Normal Mode Sleep Command Wake-Up From Interrupt Timer Expire
SGn
Figure 5. Sleep Mode to Normal Mode Operation
. Switch state change with
INT
Latch switch status on falling edge of CS
Switch state change with
CS LOW generates INT
CS LOW generates INT
CS
SGn
Rising edge of CS does not clear INT because state change occurred while CS was LOW Switch closed "1" 1 Switch Status Command
Switch open "0"
SGn Bit in SPI Word
1 Switch Status Command
0 Switch Status Command
0 Switch Status Command
1 Switch Status Command
0 Switch Status Command
Figure 6. Normal Mode Interrupt Operation
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33972 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep / wake-up modes and a robust interface between switch contacts and a microprocessor. The 33972 replaces many of the discrete components required when interfacing to microprocessorbased systems while providing switch ground offset protection, contact wetting current, and system wake-up. The 33972 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up /interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls.
FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS)
The system MCU selects the 33972 to receive communication using the chip select (CS) pin. With the CS in a logic LOW state, command words may be sent to the 33972 via the serial input (SI) pin, and switch status information can be received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output, latches the state of the INT pin, and the state of the external switch inputs. Rising edge of the CS initiates the following operation: 1. Disables the SO driver (high impedance) 2. INT pin is reset to logic [1], except when additional switch changes occur during CS LOW. (See Figure 6 on page 9.) 3. Activates the received command word, allowing the 33972 to act upon new data from switch inputs. To avoid any spurious data, it is essential the HIGH-toLOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. Internal to the 33972 device is an active pullup to VDD on CS. In Sleep mode the negative edge of CS (VDD applied) will wake up the 33972 device. Data received from the device during CS wake-up may not be accurate.
SPI SLAVE IN (SI)
The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic HIGH state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device.
SPI SLAVE OUT (SO)
The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic LOW state. All open switches are reported as zero, all closed switches are reported as one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO pin. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI / SO shifting of the data follows a first-in, first-out protocol, with both input and output words transferring the most significant bit (MSB) first.
iNTERRUPT (INT)
The INT pin is an interrupt output from the 33972 device. The INT pin is an open-drain output with an internal pullup to VDD. In Normal mode, a switch state change will trigger the INT pin (when enabled). The INT pin and INT bit in the SPI register are latched on the falling edge of CS. This permits the MCU to determine the origin of the interrupt. When two 33972 devices are used, only the device initiating the interrupt will have the INT bit set. The INT pin is cleared on the rising edge of CS. The INT pin will not clear with rising edge of CS if a switch contact change has occurred while CS was LOW. In a multiple 33972 device system with WAKE HIGH and VDD on (Sleep mode), the falling edge of INT will place all 33972s in Normal mode.
SYSTEM CLOCK (SCLK)
The system clock (SCLK) pin clocks the internal shift register of the 33972. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO pin shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic LOW state whenever CS makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin is tri-state.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
WAKE-UP (WAKE)
The WAKE pin is an open-drain output and a wake-up input. The pin is designed to control a power supply Enable pin. In the Normal mode, the WAKE pin is LOW. In the Sleep mode, the WAKE pin is HIGH. The WAKE pin has a pullup to the internal + 5.0 V supply. In Sleep mode with the WAKE pin HIGH, falling edge of WAKE will place the 33972 in Normal mode. In Sleep mode with VDD applied, the INT pin must be HIGH for negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect WAKE operation.
PROGRAMMABLE SWITCHES (SP0 : SP7)
The 33972 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 6 through Table 11 in the functional Device Operation section of this datasheet beginning on page 12. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device.
BATTERY INPUT (VPWR)
The VPWR pin is battery input and Power-ON Reset to the 33972 IC. The VPWR pin requires external reverse battery and transient protection. Maximum input voltage on VPWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR pin.
SWITCH-TO-GROUND INPUTS (SG0 : SG13)
The SGn pins are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 6 through Table 11 in the functional Device Operation section of this datasheet beginning on page 12. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR pin. Transient battery voltages greater than 40 V must be clamped by an external device.
VOLTAGE DRAIN SUPPLY (VDD)
The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive SO output and the pullup current for CS and INT pins. VDD must be applied for wake-up from negative edge of CS or INT.
GROUND (GND)
The GND pin provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES MCU INTERFACE DESCRIPTION
The 33972 device directly interfaces to a 3.3 V or 5.0 V microcontroller unit (MCU). SPI serial clock frequencies up to 6.0 MHz may be used for programming and reading switch input status (production tested at 4.16 MHz). Figure 7 illustrates the configuration between an MCU and one 33972. Serial peripheral interface (SPI) data is sent to the 33972 device through the SI input pin. As data is being clocked into the SI pin, status information is being clocked out of the device by the SO output pin. The response to a SPI command will always return the switch status, interrupt flag, and thermal flag. Input switch states are latched into the SO register on the falling edge of the chip select (CS) pin. Twenty-four bits are required to complete a transfer of information between the 33972 and the MCU. MC68HCXX Microcontroller
MOSI Shift Register MISO SCLK Parallel Ports INT SO SCLK CS INT SI
33972
33972
SI SO SCLK
MC68HCXX Microcontroller
MOSI Shift Register MISO SI SO
33972
CS INT
24-Bit Shift Register
Figure 8. SPI Parallel Interface with Microprocessor
SCLK Receive Buffer CS Parallel Ports INT INT Shift Register MISO SCLK Parallel Ports INT SO SCLK CS INT To Logic
MC68HCXX Microcontroller
MOSI SI
33972
Figure 7. SPI Interface with Microprocessor Two or more 33972 devices may be used in a module system. Multiple ICs may be SPI-configured in parallel or serial. Figures 8 and 9 show the configurations. When using the serial configuration, 48-clock cycles are required to transfer data in / out of the ICs.
33972
SI SO SCLK CS INT
Figure 9. SPI Serial Interface with Microprocessor
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
POWER SUPPLY
The 33972 is designed to operate from 5.5 V to 40 V on the VPWR pin. Characteristics are provided from 8.0 V to 16 V for the device. Switch contact currents and the internal logic supply are generated from the VPWR pin. The VDD supply pin is used to set the SPI communication voltage levels, current source for the SO driver, and pullup current on INT and CS. VDD supply may be removed from the device to reduce quiescent current. If VDD is removed while the device is in Normal mode, the device will remain in Normal mode. If VDD is removed in Sleep mode, the device will remain in Sleep mode until wake-up input is received (WAKE HIGH to LOW, switch input or interrupt timer expires). Removing VDD from the device disables SPI communication and will not allow the device to wake up from INT and CS pins.
* Falling Edge of WAKE * Falling Edge of INT (with VDD = 5.0 V and WAKE at Logic [1]) * Falling Edge of CS (with VDD = 5.0 V) * Interrupt Timer Expires Only in Normal mode with VDD applied can the registers of the 33972 be programmed through the SPI. The registers that may be programmed in Normal mode are listed below. Further explanation of each register is provided in subsequent paragraphs. *Programmable Switch Register (Settings Command ) *Wake-Up / Interrupt Register (Wake-Up / Interrupt Command ) *Wetting Current Register (Metallic Command ) *Wetting Current Timer Register (Wetting Current Timer Enable Command ) *Tri-State Register (Tri-State Command ) *Analog Select Register (Analog Command ) *Calibration of Timers (Calibration Command ) *Reset (Reset Command ) Figure 6, page 9, is a graphical description of the device operation in Normal mode. Switch states are latched into the input register on the falling edge of CS. The INT to the MCU is cleared on the rising edge of CS. However, INT will not clear on rising edge of CS if a switch has closed during SPI communication (CS LOW). This prevents switch states from being missed by the MCU.
POWER-ON RESET (POR)
Applying VPWR to the device will cause a Power-ON Reset and place the device in Normal mode. Default settings from Power-ON Reset via VPWR or Reset Command are as follows: * Programmable Switch - Set to Switch to Battery * All Inputs Set as Wake-Up * Wetting Current On (16 mA) * Wetting Current Timer On (20 ms) * All Inputs Tri-State * Analog Select 00000 (No Input Channel Selected)
PROGRAMMABLE SWITCH REGISTER
Inputs SP0 to SP7 may be programmable for switch-tobattery or switch-to-ground. These inputs types are defined using the settings command (Table 6). To set an SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set an SPn input for switch-to-ground, a logic [0] for the appropriate bit must be set. The MCU may change or update the Programmable Switch Register via software at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] will be placed in the Serial Output Response Register (Table 17, page 18).
NORMAL AND SLEEP MODES
The 33972 has two operating modes, Normal mode and Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep mode begins on page 18. Normal Mode Normal mode may be entered by the following events: * Application of VPWR to the IC * Change-of-Switch State (when enabled) Table 6. Settings Command
Settings Command 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 1 15 X 14 X 13 X
Not used 12 X 11 X 10 X 9 X 8 X 7 sp7 6 sp6
Battery/Ground Select 5 sp5 4 sp4 3 sp3 2 sp2 1 sp1 0 sp0
WAKE-UP / INTERRUPT REGISTER
The Wake-Up / Interrupt Register defines the inputs that are allowed to wake the 33972 from Sleep mode or set the INT pin LOW in Normal mode. Programming the wake-up / interrupt bit to logic [0] will disable the specific input from generating an interrupt and will disable the specific input from
waking the IC in Sleep mode (Table 7). Programming the wake-up /interrupt bit to logic [1] will enable the specific input to generate an interrupt with switch change of state and will enable the specific input as wake-up. The MCU may change or update the Wake-Up / Interrupt Register via software at any time in Normal mode.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 7. Wake-Up / Interrupt Command
Wake-Up /Interrupt Command 23 0 0 22 0 0 21 0 0 20 0 0 19 0 0 18 0 0 17 1 1 16 0 1 15 X X 14 X X 13 X 12 X 11 X 10 X 9 X Command Bits 8 X sg8 7 sp7 sg7 6 sp6 sg6 5 sp5 sg5 4 sp4 sg4 3 sp3 sg3 2 sp2 sg2 1 sp1 sg1 0 sp0 sg0
sg13 sg12 sg11 sg10 sg9
WETTING CURRENT REGISTER
The 33972 has two levels of switch contact current, 16 mA and 2.0 mA (see Figure 10). The metallic command is used to set the switch contact current level (Table 8). Programming the metallic bit to logic [0] will set the switch wetting current to 2.0 mA. Programming the metallic bit to logic [1] will set the switch contact wetting current to 16 mA. The MCU may change or update the Wetting Current Register via software at any time in Normal mode. Wetting current is designed to provide higher levels of current during switch closure. The higher level of current is designed to keep switch contacts from building up oxides that form on the switch contact surface.
Switch Contact Voltage
16 mA Switch Wetting Current
2.0 mA Switch Sustain Current 20 ms Wetting Current Timer
Figure 10. Contact Wetting and Sustain Current Table 8. Metallic Command
Metallic Command 23 0 0 22 0 0 21 0 0 20 0 0 19 0 0 18 1 1 17 0 0 16 0 1 15 X X 14 X X 13 X 12 X 11 X 10 X 9 X Command Bits 8 X sg8 7 sp7 sg7 6 sp6 sg6 5 sp5 sg5 4 sp4 sg4 3 sp3 sg3 2 sp2 sg2 1 sp1 sg1 0 sp0 sg0
sg13 sg12 sg11 sg10 sg9
WETTING CURRENT TIMER REGISTER
Each switch input has a designated 20 ms timer. The timer starts when the specific switch input crosses the comparator threshold (4.0 V). When the 20 ms timer expires, the contact current is reduced from 16 mA to 2.0 mA. The wetting current timer may be disabled for a specific input. When the timer is disabled, 16 mA of current will continue to flow through the Table 9. Wetting Current Timer Enable Command
Wetting Current Timer Commands 23 0 0 22 0 0 21 0 0 20 0 0 19 0 1 18 1 0 17 1 0 16 1 0 15 X X 14 X X 13 X 12 X 11 X
closed switch contact. With multiple wetting current timers disabled, power dissipation for the IC must be considered. The MCU may change or update the Wetting Current Timer Register via software at any time in Normal mode. This allows the MCU to control the amount of time wetting current is applied to the switch contact. Programming the wetting current timer bit to logic [0] will disable the wetting current timer. Programming the wetting current timer bit to logic [1] will enable the wetting current timer (Table 9).
Command Bits 10 X 9 X 8 X sg8 7 sp7 sg7 6 sp6 sg6 5 sp5 sg5 4 sp4 sg4 3 sp3 sg3 2 sp2 sg2 1 sp1 sg1 0 sp0 sg0
sg13 sg12 sg11 sg10 sg9
TRI-STATE REGISTER
The tri-state command is use to set the SPn or SGn input node as high impedance (Table 10). By setting the Tri-State Register bit to logic [1], the input will be high impedance
regardless of the metallic command setting. The comparator on each input remains active. This command allows the use of each input as a comparator with a 4.0 V threshold. The MCU may change or update the Tri-State Register via software at any time in Normal mode.
33972
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 10. Tri-State Command
Tri-State Commands 23 0 0 22 0 0 21 0 0 20 0 0 19 1 1 18 0 0 17 0 1 16 1 0 15 X X 14 X X 13 X 12 X 11 X 10 X Command Bits 9 X 8 X sg8 7 sp7 sg7 6 sp6 sg6 5 sp5 sg5 4 sp4 sg4 3 sp3 sg3 2 sp2 sg2 1 sp1 sg1 0 sp0 sg0
sg13 sg12 sg11 sg10 sg9
ANALOG SELECT REGISTER
The analog voltage on switch inputs may be read by the MCU using the analog command (Table 11). Internal to the IC is a 22-to-1 analog multiplexer. The voltage present on the selected input pin is buffered and made available on the AMUX output pin. The AMUX output pin is clamped to a maximum of VDD volts regardless of the higher voltages present on the input pin. After an input has been selected as the analog, the corresponding bit in the next SO data stream will be logic [0]. When selecting a channel to be read as analog, the user must also set the desired current (16 mA, 2.0 mA, or high impedance). Setting bit 6 and bit 5 to 0,0 Table 11. Analog Command
Analog Command 23 0 22 0 21 0 20 0 19 0 18 1 17 1 16 0 15 X 14 X 13 X
selects the input as high impedance. Setting bit 6 and bit 5 to 0,1 selects 2.0 mA, and 1,0 selects 16 mA. Setting bit 6 and bit 5 to 1,1 in the Analog Select Register is not allowed and will place the input as an analog input with high impedance. Analog currents set by the analog command are pullup currents for all SGn and SPn inputs (Table 11). The analog command does not allow pulldown currents on the SPn inputs. Setting the current to 16 mA or 2.0 mA may be useful for reading sensor inputs. Further information is provided in the Typical Applications section of this datasheet beginning on page 20. The MCU may change or update the Analog Select Register via software at any time in Normal mode.
Not used 12 X 11 X 10 X 9 X 8 X 7 X
Current Select 6 5
Analog Channel Select 4 0 3 0 2 0 1 0 0 0
16 mA 2.0 mA
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 12. Analog Channel
Bits 43210 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Analog Channel Select No Input Selected SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7
CALIBRATION OF TIMERS
In cases where an accurate time base is required, the user may calibrate the internal timers using the calibration command (Table 13). After the 33972 device receives the calibration command, the device expects 512 s logic [0] calibration pulse on the CS pin. The pulse is used to calibrate the internal clock. No other SPI pins should transition during Table 13. Calibration Command
Calibration Command 23 0 22 0 21 0 20 0 19 1 18 0 17 1 16 1 15 X 14 X 13 X 12 X
this 512 s calibration pulse. Because the oscillator frequency changes with temperature, calibration is required for an accurate time base. Calibrating the timers has no affect on the quiescent current measurement. The calibration command simply makes the time base more accurate. The calibration command may be used to update the device on a periodic basis.
Command Bits 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
RESET
The reset command resets all registers to Power-ON Reset (POR) state. Refer to Table 15, page 17, for POR Table 14. Reset Command
Reset Command 23 0 22 1 21 1 20 1 19 1 18 1 17 1 16 1 15 X 14 X 13 X 12 X
states or the paragraph entitled Power-ON Reset (POR) on page 13 of this datasheet.
Command Bits 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X
SPI COMMAND SUMMARY
Table 15 below provides a comprehensive list of SPI commands recognized by the 33972 and the reset state of each register. Table 16 and Table 17 contain the Serial Table 15. SPI Command Summary
MSB
23 Switch Status Command Settings Command Bat = 1, Gnd = 0 (Default state = 1) Wake-Up/Interrupt Bit Wake-Up = 1 Non-Wake-Up = 0 (Default state = 1) Metallic Command Metallic = 1 Non-metallic = 0 (Default state = 1) Analog Command Wetting Current Timer Enable Command Timer ON = 1 Timer OFF = 0 (Default state = 1) Tri-State Command Input Tri-State = 1 Input Active = 0 (Default state = 1) Calibration Command (Default state - 'uncalibrated) Sleep Command (Refer to Sleep Mode on page 18.) Reset Command SO Response Will Always Send 0 22 0 21 0
Output (SO) data for input voltages greater or less than the threshold level. Open switches are always indicated with a logic [0], closed switches are indicated with logic [1].
Command Bits
20 0 19 0 18 0 17 0 16 0 15 X 14 X 13 X 12 X 11 X 10 X
Setting Bits
9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X
LSBI
0 X
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
1 1 0 0
0 1 0 1
X X X X
X X X X
X
X
X
X
X
X SG8 X SG8
SP7 SG7 SP7 SG7
SP6 SG6 SP6 SG6
SP5 SG5 SP5 SG5
SP4 SG4 SP4 SG4
SP3 SG3 SP3 SG3
SP2 SG2 SP2 SG2
SP1 SG1 SP1 SG1
SP0 SG0 SP0 SG0
SG13 SG12 SG11 SG10 SG9 X X X X X
SG13 SG12 SG11 SG10 SG9
0 0
0 0
0 0
0 0
0 0
1 1
1 1
0 1
X X
X X
X X
X X
X X
X X
X X
X X
X SP7
16mA 2.0mA 0 0 SP6 SP5
0 SP4
0 SP3
0 SP2
0 SP1
0 SP0
0
0
0
0
1
0
0
0
X
X
SG13 SG12 SG11 SG10 SG9
SG8
SG7
SG6
SG5
SG4
SG3
SG2
SG1
SG0
0 0
0 0
0 0
0 0
1 1
0 0
0 1
1 0
X X
X X
X
X
X
X
X
X SG8
SP7 SG7
SP6 SG6
SP5 SG5
SP4 SG4
SP3 SG3
SP2 SG2
SP1 SG1
SP0 SG0
SG13 SG12 SG11 SG10 SG9
0
0
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
int int int scan scan scan timer timer timer timer timer timer X SG5 X SG4 X SG3 X SG2 X SG1 X SG0
0 them flg
1 int flg
1 SP7
1 SP6
1 SP5
1 SP4
1 SP3
1 SP2
X SP1
X
X
X
X
X
X
X SG8
X SG7
X SG6
SP0 SG13 SG12 SG11 SG10 SG9
33972
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 16. Serial Output (SO) Bit Data
Type of Input SP Input Programmed Switch to Ground Switch to Ground Switch to Battery Switch to Battery SG N/A N/A Voltage on Input Pin SPn < 4.0 V SPn > 4.0 V SPn < 4.0 V SPn > 4.0 V SGn < 4.0 V SGn > 4.0 V SO SPI Bit 1 0 0 1 1 0
Table 17. Serial Output (SO) Response Register
SO Response Will Always Send them flg int flg SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
EXAMPLE OF NORMAL MODE OPERATION
The operation of the device in Normal Mode is defined by the states of the programmable internal control registers. A typical application may have the following settings: * Programmable Switch - Set to Switch-to-Ground * All Inputs Set as Wake-Up * Wetting Current On (16 mA) * Wetting Current Timer On (20 ms) * All inputs Tri-State-Disabled (comparator is active) * Analog select 00000 (no input channel selected) With the device programmed as above, an interrupt will be generated with each switch contact change of state (open-toclose or close-to-open) and 16 mA of contact wetting current will be source for 20 ms. The INT pin will remain LOW until switch status is acknowledged by the microprocessor. It is critical to understand INT will not be cleared on the rising edge of CS if a switch closure occurs while CS is LOW. The maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. Figure 6, page 9, shows the interaction between changing input states and the INT and CS pins. If desired the user may disable interrupts (wake up/ interrupt command) from the 33972 device and read the switch states on a periodic basis. Switch activation and deactivation faster than the MCU read rate will not be acknowledged. The 33972 device will exit the Normal mode and enter the Sleep mode only with a valid sleep command.
SLEEP MODE
Sleep mode is used to reduce system quiescent currents. Sleep mode may be entered only by sending the sleep command. All register settings programmed in Normal mode will be maintained in Sleep mode. The 33972 will exit Sleep mode and enter Normal mode when any of the following events occur: * Input Switch Change of State (when enabled) * Interrupt Timer Expire * Falling Edge of WAKE * Falling Edge of INT (with VDD = 5.0 V and WAKE at Logic [1]) * Falling Edge of CS (with VDD = 5.0 V) * Power-ON Reset (POR) The VDD supply may be removed from the device during Sleep mode. However removing VDD from the device in Sleep mode will disable a wake-up from falling edge of INT and CS. Note In cases where CS is used to wake the device, the first SO data message is not valid. The sleep command contains settings for two programmable timers for Sleep mode, the interrupt timer and the scan timer, as shown in Table 18 The interrupt timer is used as a periodic wake-up timer. When the timer expires, an interrupt is generated and the device enters Normal mode. Note The interrupt timer in the 33972 device may be disabled by programming the interrupt bits to logic [1 1 1]. Table 19 shows the programmable settings of the Interrupt timer.
Table 18. Sleep Command
Sleep Command 23 0 22 0 21 0 20 0 19 1 18 1 17 0 16 0 15 X 14 X 13 X 12 X 11 X 10 X 9 X Command Bits 8 X 7 X 6 X 5 int timer 4 int timer 3 int timer 2 scan timer 1 scan timer 0 scan timer
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 19. Interrupt Timer
Bits 543 000 001 010 011 100 101 110 111 Interrupt Period 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s 2.048 s No interrupt wake-up
Figure 5, page 9, is a graphical description of how the 33972 device exits Sleep mode and enters Normal mode. Notice that the device will exit Sleep mode when the interrupt timer expires or when a switch change of state occurs. The falling edge of INT triggers the MCU to wake from Sleep state. Figure 11 illustrates the current consumed during Sleep mode. During the 125 s, the device is fully active and switch states are read. The quiescent current is calculated by integrating the normal running current over scan period plus approximately 60 A.
The scan timer sets the polling period between input switch reads in Sleep mode. The period is set in the sleep command and may be set to 000 (no period) to 111 (64 ms). In Sleep mode when the scan timer expires, inputs will behave as programmed prior to sleep command. The 33972 will wake up for approximately 125 s and read the switch inputs. At the end of the 125 s, the input switch states are compared with the switch state prior to sleep command. When switch state changes are detected, an interrupt (when enabled; refer to wake-up / interrupt command description on page 14) is generated and the device enters Normal mode. Without switch state changes, the 33972 will reset the scan timer, inputs become tri-state, and the Sleep mode continues until the scan timer expires again. Table 20 shows the programmable settings of the Scan timer. Table 20. Scan Timer
Bits 210 000 001 010 011 100 101 110 111 Scan Period No Scan 1.0 ms 2.0 ms 4.0 ms 8.0 ms 16 ms 32 ms 64 ms
I=V/R or 0.270 V/100 =2.7 I=V/Ror 0.270V/100ohm = 2.7mA mA
Inputs active for 125 us 125 32 out out of sms of 32 ms
Inputs active for
I=V/R or I=V/R or 6mV/100ohm = 60 uA 6.0 mV/100 =60 A
Figure 11. Sleep Current Waveform
TEMPERATURE MONITOR
With multiple switch inputs closed and the device programmed with the wetting current timers disabled, considerable power will be dissipated by the IC. For this reason temperature monitoring has been implemented. The temperature monitor is active in the Normal mode only. When the IC temperature is above the thermal limit, the temperature monitor will do all of the following: * Generate an interrupt. * Force all 16 mA pullup and pulldown current sources to revert to 2.0 mA current sources. * Maintain the 2.0 mA current source and all other functionality. * Set the thermal flag bit in the SPI output register. The thermal flag bit in the SPI word will be cleared on rising edge of CS provided the die temperature has cooled below the thermal limit. When die temperature has cooled below thermal limit, the device will resume previously programmed settings.
Note The interrupt and scan timers are disabled in the Normal mode.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
The 33972's primary function is the detection of open or closed switch contacts. However, there are many features that allow the device to be used in a variety of applications. The following is a list of applications to consider for the IC: Sensor Power Supply Switch Monitor for Metallic or Elastomeric Switches Analog Sensor Inputs (Ratiometric) Power MOSFET / LED Driver and Monitor Multiple 33972 Devices in a Module System The following paragraphs describe the applications in detail.
METALLIC / ELASTOMERIC SWITCH
Metallic switch contacts often develop higher contact resistance over time owing to contact corrosion. The corrosion is induced by humidity, salt, and other elements that exist in the environment. For this reason the 33972 provides two settings for contacts. When programmed for metallic switches, the device provides higher wetting current to keep switch contacts free of oxides. The higher current occurs for the first 20 ms of switch closure. Where longer duration of wetting current is desired, the user may send the wetting current timer command and disable the timer. Wetting current will be continuous to the closed switch. After the time period set by the MCU, the wetting current timer command may be sent again to enable the timer. The user must consider power dissipation on the device when disabling the timer. (Refer to the paragraph entitled Temperature Monitor, page 19.) To increase the amount of wetting current for a switch contact, the user has two options. Higher wetting current to a switch may be achieved by paralleling SGn or SPn inputs. This will increase wetting current by 16 mA for each input added to the switch contact. The second option is to simply add an external resistor pullup to the VPWR supply for switchto-ground inputs or a resistor to ground for a switch-to-battery input. Adding an external resistor has no effect on the operation of the device. Elastomeric switch contacts are made of carbon and have a high contact resistance. Resistance of 1.0 k is common. In applications with elastomeric switches, the pullup and pulldown currents must be reduced to prevent excessive power dissipation at the contact. Programming for a lower current settings is provided in the functional Device Operation Section beginning on page 12 under Table 8, Metallic Command.
SENSOR POWER SUPPLY
Each input may be used to supply current to sensors external to a module. Many sensors such as Hall effect, pressure sensors, and temperature sensors require a supply voltage to power the sensor and provide an open collector or analog output. Figure 12 shows how the 33972 may be used to supply power and interface to these types of sensors. In an application where the input makes continuous transitions, consider using the wake-up / interrupt command to disable the interrupt for the particular input.
VBAT SP0 SP1 VBAT SP7
33972
VPWR VDD WAKE SI SG0 SG1 VPWR VPWR 16 mA 2.0 mA SCLK CS SO INT MOSI SCLK CS MISO INT
VDD
MCU
ANALOG SENSOR INPUTS (RATIOMETRIC)
The 33972 features a 22-to-1 analog multiplexer. Setting the binary code for a specific input in the analog command allows the microcontroller to perform analog to digital conversion on any of the 22 inputs. On rising edge of CS the multiplexer connects a requested input to the AMUX pin. The AMUX pin is clamped to max of VDD volts regardless of the higher voltages present on the input pin. After an input has been selected as the analog, the corresponding bit in the next SO data stream will be logic [0]. The input pin, when selected as analog, may be configured as analog with high impedance, analog with 2.0 mA pullup, or analog with 16 mA pullup. Figure 13, page 21, shows how the 33972 may be used to provide a ratiometric reading of variable resistive input.
16 mA
SG12 VPWR VPWR
Hall-Effect Sensor Reg
X
16 mA SG13
2.0 mA
2.5 k 2.5 k
IOC[7:0]
Input Capture Timer Port
Figure 12. Sensor Power Supply
33972
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS INTRODUCTION
VBAT SP0 SP1
33972
VPWR VDD SP7 WAKE SI SG0 SG1 VPWR VPWR 16 mA SG12 VPWR VPWR 16 mA 2.0 mA 2.0 mA SCLK CS SO INT AMUX MOSI SCLK CS MISO INT AN0 Analog Ports VDD
conversion may be obtained. Using the equation yields the following: I1 x R1 x 225 ADC = I2 x R2
MCU
VBAT
ADC =
2.0 mA x 2.0 k 2.0 mA x 2.39 k
x 225
ADC = 213 counts The ADC value of 213 counts is the value with 0% error (neglecting the resistor tolerance and AMUX input offset voltage). Now we can calculate the count value induced by the mismatch in current sources. From a sample device the maximum current source was measured at 2.05 mA and minimum current source was measured at 1.99 mA. This yields 3% error in A / D conversion. The A / D measurement will be as follows: 1.99 mA x 2.0 k 2.05 mA x 2.39 k ADC = 207 counts This A / D conversion is 3% low in value. The error correction factor of 1.03 may be used to correct the value: ADC = 207 counts x 1.03
2.0 mA R1
I1
Analog Sensor or Analog Switch SG13
I2 2.0 mA
4.54 V to 5.02 V R2 VREF(H) VREF(L)
ADC =
x 225
2.39 k 0.1%
Figure 13. Analog Ratiometric Conversion To read a potentiometer sensor, the wiper should be grounded and brought back to the module ground, as illustrated in Figure 13. With the wiper changing the impedance of the sensor, the analog voltage on the input will represent the position of the sensor. Using the Analog feature to provide 2.0 mA of pullup current to an analog sensor may induce error due to the accuracy of the current source. For this reason, a ratiometric conversion must be considered. Using two current sources (one for the sensor and one to set the reference voltage to the A / D converter) will yield a maximum error (owing to the 33972) of 4%. Higher accuracy may be achieved through module level calibration. In this example, we use the resistor values from Figure 13 and assume the current sources are 4% from each other. The user may use the module end-of-line tester to calculate the error in the A / D conversion. By placing a 2.0 k, 0.1% resistor in the end-of-line test equipment and assuming a perfect 2.0 mA current source from the 33972, a calculated A / D ADC = 213 counts An error correction factor may then be stored in E2 memory and used in the A / D calculation for the specific input. Each input used as analog measurement will have a dedicated calibrated error correction factor.
POWER MOSFET / LED DRIVER AND MONITOR
Because of the flexible programming of the 33972 device, it may be used to drive small loads like LEDs or MOSFET gates. It was specifically designed to power up in the Normal mode with the inputs tri-state. This was done to ensure the LEDs or MOSFETs connected to the 33972 power up in the off-state. The Switch Programmable (SP0 - SP7) inputs have a source-and-sink capability, providing effective MOSFET gate control. To complete the circuit, a pulldown resistor should be used to keep the gate from floating during the Sleep modes. Figure 14, page 22, shows an application where the SG0 input is used to monitor the drain-to-source voltage of the external MOSFET. The 1.5 k resistor is used to set the drain-to-source trip voltage. With the 2.0 mA current source enabled, an interrupt will be generated when the drain-to-source voltage is approximately 1.0 V.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS INTRODUCTION
VBAT
VPWR VPWR 16 mA 2.0 mA
SG0
The analog command may be used to monitor the drain voltage in the MOSFET ON state. By sourcing 2.0 mA of current to the 1.5 k resistor, the analog voltage on the SGn pin will be approximately: VSGn = ISGn x 1.5 k + VDS As the voltage on the drain of the MOSFET increases, so does the voltage on the SGn pin. With the SGn pin selected as analog, the MCU may perform the A / D conversion. Using this method for controlling unclamped inductive loads is not recommended. Inductive flyback voltages greater than VPWR may damage the IC. The SP0 : SP7 pins of this device may also be used to send signals from one module to another. Operation is similar to the gate control of a MOSFET. * For LED applications a resistor in series with the LED is recommended but not required. The switch-to-ground inputs are recommended for LED application. To drive the LED use the following commands: * wetting current timer enable command - Disable SGn wetting current timer. * metallic command - Set SGn to 16 mA. From this point forward the LED may be turned on and off using the tri-state command : * tri-state command - Disable tri-state for SGn (LED ON). * tri-state command - Enable tri-state for SGn (LED OFF). These parameters are easily programmed via SPI commands in Normal mode.
The sequence of commands (from Normal mode with inputs tri-state) required to set up the device to drive a MOSFET are as follows: * wetting current timer enable command - Disable SPn wetting current timer (refer to Table 9, page 14). * metallic command - Set SPn to 16 mA or 2.0 mA gate drive current (refer to Table 8, page 14). * settings command - Set SPn as switch-to-battery (refer to Table 6, page 13). * tri-state command - Disable tri-state for SPn (refer to Table 10, page 15). After the tri-state command has been sent (tri-state disable), the MOSFET gate will be pulled to ground. From this point forward the MOSFET may be turned on and off by sending the settings command : * settings command - SPn as switch-to-ground (MOSFET ON). * settings command - SPn as switch-to-battery (MOSFET OFF). Monitoring of the MOSFET drain in the OFF state provides open load detection. This is done by using an SGn input comparator. With the SGn input in tri-state, the load will pull up the SGn input to battery. With open load the SGn pin is pulled down to ground through an external resistor. The open load is indicated by a logic [1] in the SO data bit.
33972
22
LOAD 1.5 k 100 k SG0 SP0 SG13
AMUX
4.0 V Ref + To SPI
Comparator VPWR VPWR 16 mA 2.0 mA
SG0
16 mA
To SPI 4.0 V + Ref Comparator 2.0 mA
VPWR VPWR 16 mA 2.0 mA
SG13
4.0 V Ref
+ -
To SPI
Comparator
Figure 14. MOSFET or LED Driver Output
MULTIPLE 33972 DEVICES IN A MODULE SYSTEM
Connecting power to the 33972 and the MCU for Sleep mode operation may be done in several ways. Table 21 shows several system configurations for power between the MCU and the 33972 and their specific requirements for functionality. Table 21. Sleep Mode Power Supply
MCU VDD 5.0 V 5.0 V 0V 33972 VDD 5.0 V 0V 5.0 V Comments All wake-up conditions apply. (Refer to Sleep Mode, page 18.) SPI wake-up is not possible. Sleep mode not possible. Current from CS pullup will flow through MCU to VDD that has been switched off. Negative edge of CS will put 33972 in Normal mode. SPI wake-up is not possible.
0V
0V
Multiple 33972 devices may be used in a module system. SPI control may be done in parallel or serial. However when parallel mode is used, each device is addressed independently (refer to MCU Interface Description, page 12).
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS INTRODUCTION
Therefore when sending the sleep command, one device will enter sleep before the other. For multiple devices in a system, it is recommended that the devices are controlled in serial (S0 from first device is connected to SI of second device). With two devices, 48 clock pulses are required to shift data in. When the WAKE feature is used to enable the power supply, both WAKE pins should be connected to the enable pin on the power supply. The INT pins may be connected to one interrupt pin on the MCU or may have their own dedicated interrupt to the MCU. The transition from Normal to Sleep mode is done by sending the sleep command. With the devices connected in serial and the sleep command sent, both will enter Sleep mode on the rising edge of CS. When Sleep mode is entered, the WAKE pin will be logic [1]. If either device wakes up, the WAKE pin will transition LOW, waking the other device. A condition exists where the MCU is sending the sleep command (CS logic [0]) and a switch input changes state. With this event the device that detects this input will not transition to Sleep mode, while the second device will enter Sleep mode. In this case two switch status commands must be sent to receive accurate switch status data. The first switch status command will wake the device in Sleep mode. Switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 V input comparator threshold. This time is dependant on the impedance of SGn or SPn node. The second switch status command will provide accurate switch status information. It is recommended that software wait 10 ms to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. With all switch states acknowledged by the MCU, the sleep sequence may be initiated. All parameters for Sleep mode should be updated prior to sending the sleep command.
The 33972 IC has an internal 5.0 V supply from VPWR pin. A POR circuit monitors the internal 5.0 V supply. In the event of transients on the VPWR pin, an internal reset may occur. Upon reset the 33972 will enter Normal mode with the internal registers as defined in Table 15, page 17. Therefore it is recommended that the MCU periodically update all registers internal to the IC.
USING THE WAKE FEATURE
The 33972 provides a WAKE output and wake-up input designed to control an enable pin on system power supply. While in the Normal mode, the WAKE output is LOW, enabling the power supply. In the Sleep mode, the WAKE pin is HIGH, disabling the power supply. The WAKE pin has a passive pullup to the internal 5.0 V supply but may be pulled up through a resistor to VPWR supply (see Figure 16, page 24) When the WAKE output is not used the pin should be pulled up to the VDD supply through a resistor as shown in Figure 15, page 24. During the Sleep mode, a switch closure will set the WAKE pin LOW, causing the 33972 to enter the Normal mode. The power supply will then be activated, supplying power to the VDD pin and the microprocessor and the 33972. The microprocessor can determine the source of the wake-up by reading the interrupt flag.
COST AND FLEXIBILITY
Systems requiring a significant number of switch interfaces have many discrete components. Discrete components on standard PWB consume board space and must be checked for solder joint integrity. An integrated approach reduces solder joints, consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS INTRODUCTION
VDD VBAT
VBAT SP0 SP1
Power Supply 33972 VPWR VPWR VDD VDD
SP7 WAKE CS SG0 SG1 INT SI SO SCLK SG12 AMUX
VDD
VBAT
MC68HCXX Microprocessor
CS INT MOSI MISO
SCLK
AN0
SG13
Figure 15. Power Supply Active in Sleep Mode VDD VBAT
VBAT SP0 SP1 VBAT SP7 CS SG0 SG1 INT SI SO SCLK SG12 AMUX CS INT MOSI MISO WAKE
Power Supply 33972 VPWR VDD VPWR Enable
VDD
VDD
MC68HCXX Microprocessor
SCLK
AN0
SG13
Figure 16. Power Supply Shutdown in Sleep Mode
33972
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below.
DWB SUFFIX EW SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY PLASTIC PACKAGE 98ARH99137A
33972
Analog Integrated Circuit Device Data Freescale Semiconductor
25
PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
33972
26
Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 4.0
DATE 2/2006
DESCRIPTION OF CHANGES
* * * * * * * * * *
Converted to Freescale format Added PC33972A version Changed Figure 15, Power Supply Active in Sleep Mode Changed Figure 16, Power Supply Shutdown in Sleep Mode Updated Outline Drawing for package Added MC33972T devices. Updated StatiC Electrical Characteristics on page 6 with 33972T parameters. Changed Human Body Model parameters in Maximum Ratings table. Replaced Part Number MC33972TEW/R2 with MCZ33972TEW/R2 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. Restated note (6) Changed Part Number MCZ33972TEW/R2 with MC33972TEW/R2 Removed all references to the 33972T device. Removed the MC33972TDWB/R2, MC33972TEW/R2, and PC33972AEW/R2 from the ordering information. Added MCZ33972AEW/R2 to the ordering information.
5.0 6.0 7.0
6/2006 7/2006 11/2006
* Update to the prevailing Freescale form and style.
8.0 9.0
12/2006 4/2007
* * * * *
33972
Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33972 Rev. 9.0 4/2007

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